1. Field of the Invention
The present invention relates to a substrate and a process for fabricating the same. More particularly, the present invention relates to a substrate having contacts separated by a minute distance and process for fabricating the same.
2. Description of the Related Art
In the semiconductor industry, the manufacturing process of Integrated Circuit (IC) can be divided into three steps: fabricating electronic devices, such as transistor or metal oxide semiconductor (MOS), etc., forming patterned fine circuits to electrically connect the electronic devices with each other, and packaging a chip. The main objective of packaging a chip is to protect a chip from moisture and impurities and to electrically connect a chip to a substrate. Thereafter, the chip is electrically connected to a substrate either through conductive wires or bumps and then the entire chip together with the conductive wires or bumps is enclosed using some packaging material for protecting the chip and the electrical connections between the chip and the substrate.
However, in a flip chip process, bumps are attached to the chip before the chip joins with the substrate via the bumps. Hence, the pitch between neighboring bumps as well as the pitch between neighboring contacts on the substrate will directly affect the total number of input/output terminals. The number of input/output terminals between the chip and the substrate will also affect the size of the chip. As electronic technologies continue to advance, more multi-functional, personalized electronic products are developed in the market. To gain a competitive edge in the market, most electronic manufacturers aim at miniaturizing and lightening their products. Hence, most chips and substrates are designed to occupy as small area and have as small a thickness as possible. Yet, squeezing more input/output terminals into the chip and the substrate for electrical connection demands a reduction of the pitch between neighboring contacts on the substrate as well as the pitch between neighboring bumps.
In the following, a method of fabricating a conventional substrate and some of the limitations in fabricating process is described. FIGS. 1A through 1G are magnified schematic cross-sectional views showing the progression of steps for fabricating a conventional substrate.
As shown in FIG. 1A, a semi-finished substrate 110 is provided. The substrate 110 comprises a plurality of insulating layers 111, 112, 113, 114, 115 and a multiple of patterned metallic layers 121, 122, 123, 124, alternately laid over each other. The semi-finished substrate 110 also has at least a through hole 131 that passes through the substrate 110. The wall of the through hole 131 has a conductive material layer 132 for electrically connecting the patterned metallic layers 121, 122, 123, 124. The insulating layers 111 and 115 have a plurality of openings 133 and 134 that exposes the patterned circuit layers 121 and 124 respectively.
Thereafter, as shown in FIG. 1B, a roughening process is carried out to roughen the exposed surface of the insulating layers 111 and 115. Next, an electroless plating method can be used to form a seed layer 151 and 152 on the insulating layers 111 and 115, on the sidewalls of the openings 133 and 134 in the insulating layers 111 and 115 and on the patterned circuit layers 121 and 124, respectively.
As shown in FIG. 1C, photoresist layers 153 and 154 are formed over the seed layers 151 and 152 respectively. A plurality of patterned openings 155, 156 that passes through the photoresist layers 153, 154 and exposes the seed layers 151, 152 is formed. The patterned openings 155, 156 include contact pattern (the patterned openings 155, 156 in FIG. 1C) and circuit pattern.
As shown in FIG. 1D, an electroplating operation is performed to form patterned metallic layers 157, 158 on the seed layer 151, 152 exposed by the patterned openings 155, 156 in the photoresist layers 153, 154. The patterned metallic layers 157, 158 include contact pattern (the patterned metallic layer 157, 158 in FIG. 1D) and circuit pattern. Thereafter, the photoresist layers 153, 154 is removed from the seed layers 151, 152 to expose the seed layers 151, 152 and form a structure as shown in FIG. 1E. Using the patterned metallic layers 157, 158 as an etching mask, the exposed seed layers 151, 152 are removed so that only the seed layers 151, 152 underneath the patterned metallic layers 157, 158 is retained and the insulating layers 111, 115 are exposed to the outside as shown in FIG. 1F.
As shown in FIG. 1G, a screen printing operation is carried out to form solder mask layers 159, 160 over the insulating layers 111, 115. The solder mask layers 159, 160 covers the circuit portion (not shown) of the patterned metallic layers 157, 158. Furthermore, the solder mask layers 159, 160 also have a plurality of openings 161, 162 that pass through the solder mask layers 159, 160 and exposes the contact portion (the patterned metallic layers 157, 158 in FIG. 1G) of the patterned metallic layers 157, 158. After completing the fabrication of the substrate 100, the substrate 100 is able to electrically bond with the bumps (not shown) on a flip chip via the contacts on the patterned metallic layer 157.
In the aforementioned fabrication process, size and pitch of the contacts will be directly affected by the tolerance of the patterned opening 155 in the photoresist layer 153 and the tolerance of the opening 161 in the solder mask layer 159. Hence, in the fabrication of the contacts, the photoresist layer 153 must have a larger patterned opening 155 and the solder mask layer 159 must have a larger opening 161. Ultimately, the contact portion of the patterned metallic layer 157 has to be larger just to ensure the formation of a proper junction between the bumps on a flip chip and the contact portion of the patterned metallic layer 157 on the substrate 100. Because the contact portion in the patterned metallic layer 157 is large, pitch between neighboring contacts in the substrate 100 must be increased. In other words, area occupation of the substrate 100 is increased. To match up with the distance of separation between the contacts in the substrate, the distance of separation between neighboring bonding pads on the chip must also be increased. Ultimately, the chip needs to occupy a larger surface area.